差分晶振

Parameter

LVPECL

LVDS

3.3V

2.5v

3.3V

2.5V

Supply Voltage Variation(V_DD)

V_DD±10%

V_DD±5%Min.

V_DD±10%

V_DD±5%Min.

Frequency Range

10~1500MHz

Supply Current

35~50mA

35~45mA

Output Level  Output High

            Output Low

2.27~2.7V

1.47~1.9V

1.6V

1.45V

1.7V

0.65V

0.9V

0.9V

Transition Time:Rise/Fall Time⁺

1.0nSec Max.

Duty Cycle

45%~55%

Start Time

10mSecMax.

Tri-State(Input to Pin 2 or Pin 1)

EnableI(High voltage or floating)

Disable(Low voltage or GND)

0.7×V_DD Min

0.3×V_DD Max.

Stand by Current

18mA Max.

Output Loading

50 into VDD-2V

100

Phase  Noise

Typ.

Max.

Typ.

Max.

Typ.

Max.

Typ.

Max.

At VDD=3.3v,fout-250MHz

1KHz offset

-107

-

-107

-

-107

-

-107

-

dBc/Hz

10KHz offset

-111

-

-111

-

-111

-

-111

-

100KHz offset

-114

-

-114

-

-114

-

-114

-

1MHz offset

-125

-

-125

-

-125

-

-125

-

20MHz offset

-147

-

-147

-

-147

-

-147

-

RMS Phase Jitter(12KHz to 20MHz)

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.5

pSec